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COSC 410 Computer Architecture

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Pre-requisites: COSC 300 and 310

Introduces the underlying working principles of electronic computers. The organization and architecture of computer components are discussed. The course expounds on details of memory hierarchy, I/O organization, computer arithmetic, processor and control unit design, instruction set architecture, instruction-level parallelism, and the ways functional components interact together.

Course Outcomes
Upon successful completion of the course, the student will be able to:

1. Explain the importance of studying computer architecture.
2. Evaluate various trade-offs while designing a computer system.
3. Describe how various computer components interact in order to exchange information.
4. Explain the need for the use of memory hierarchy (cache, main memory, storage devices) to ensure the design of a balanced computer system.
5. Describe how I/O systems work.
6. Discuss the relationship between the design of a computer system and the design of an operating system to operate it.
7. Describe the fundamental principles of CPU and control unit design.
8. Evaluate various trade-offs in designing the instruction set architecture.
9. Design fast ALU circuitry.
10. Identify and evaluate various techniques for improving contemporary processor performance.

Detailed Course Outline
A. Introduction to Computer Architecture — 3 hrs
1. Importance of computer architecture
2. Architecture versus organization
3. Computer history and generations
4. Hierarchical view and operational concepts
5. Evaluating computer performance

B. Component Interconnection and Bus Structures — 3 hrs
1. Basic components and their functions
2. Interconnecting components
3. Interrupt handling
4. Bus structures and types

C. Memory Hierarchy — 12 hrs
Cache Memory — 4 hrs
1. Cache memory basics
2. Cache memory design (Mapping functions, replacement algorithms, write policies, etc.)

Main Memory and Virtual Memory — 4 hrs
1. Main memory organization and operation
2. Main memory types (static RAM, synchronous DRAM, Rambus DRAM, DDR SDRAM, and cache DRAM)
3. Virtual memory (paging, segmentation, thrashing, etc.)
4. Address translation and TLBs

Secondary Storage — 4 hrs
1. Secondary storage devices operation and performance (magnetic and optical media)
2. Evaluating various design decisions and trade-offs while designing different components of the memory hierarchy

D. I/O and Operating Systems — 6 hrs
1. I/O architecture
2. I/O types (programmed, interrupt-driven, DMA. etc.)
3. Buses (synchronous and asynchronous)
4. Interface circuits (serial and parallel)
5. Interface types (PCI, SCSI, and USB)
6. Operating systems functionalities (scheduling, memory management, etc.) and hardware support for these functions

E. The Central Processing Unit (CPU) — 7 hrs
1. Structure and functions
2. Basics of computer arithmetic
3. Integer and floating point operations (addition, subtraction, etc.)
4. Design of fast arithmetic and logic circuitry
5. Addressing modes and instruction set architecture

F. Control Unit — 4 hrs
1. The concept of micro-operations
2. Generation of control signals
3. Control unit implementation using hardwired control
4. Fundamentals of Microprogramming (micro-instruction sequencing, wide branch address, next instruction field, emulation, etc.)

G. Performance Enhancement — 5 hrs
1. Pipeline design
2. Various hazards (structural, data, and control)
3. Performance evaluation of pipeline systems
4. Instruction level parallelism
5. Multi-core chips and thread level parallelism

H. In-class examinations — 2 hrs

Total: 42 hrs

Final exam (During Final Exam Week) — 2 hrs

Grading Scale
The standard grading scale will be used:
90%+ = A;
80-89% = B;
70-79% = C;
60-69% = D;
<60% = F.

Evaluation Methods

Point Distribution. There will be three exams, outside-of-class assignments, and projects. The approximate distribution of points will be:
a. Two equal-weight class exams  35%
b. Final exam    25%
c. Assignments and projects   30%
d. Student participation   10%

Attendance Policy
Class attendance is regarded as being very important. Individual faculty members may establish penalties for excessive numbers of unexcused absences. Excused absences will be allowed for illness, family emergencies, and involvement in university activities such as sports.  The penalties specified will meet university guidelines and be distributed to students with the course syllabus on the first day of class.

Required Textbooks, Supplemental books, and Readings
Stallings, William, “Computer Organization & Architecture” 7th Edition Prentice Hall, ISBN “013-185644-8”, 2006

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  • Computer Science Department
  • Stright Hall, Room 319
    210 South Tenth Street
    Indiana, PA 15705
  • Phone: 724-357-2524
  • Fax: 724-357-2724
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  • Office Hours
  • Monday through Friday
  • 7:30 a.m. – 12:00 p.m.
  • 1:00 p.m. – 4:00 p.m.